Valid Data Filter

SystemVerilog
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1

Q. How to filter data only if valid=1 and discard other data?
Is there a better way without explicit index manipulation ?

EDA Link: EDA Playground

class valid_data_detect;
    rand bit valid[$];
    rand bit data[$];
  
  constraint vld_data_size {
     valid.size() inside {[5:8]};
     data.size() == valid.size();
     solve valid before data;
  }
      
  
endclass

module test;
  valid_data_detect datavld;
  
  
  initial begin
    datavld=new();
    datavld.randomize();
       foreach(datavld.valid[i]) begin
         $display("Before Valid=%0d, Data=%0d", datavld.valid[i], datavld.data[i]);
      end
    for(int i=0;i<=datavld.valid.size()-1;i++) begin
        if (datavld.valid[i]!=1) begin
             datavld.data.delete(i);
             datavld.valid.delete(i);
             i- -;
        end
    end
        foreach(datavld.valid[i]) begin
             $display("After Valid=%0d, Data=%0d", datavld.valid[i], datavld.data[i]);
        end
  
  end
endmodule
2

You could use the find() method, though I don’t think it is any better.

class valid_data_detect;
  rand bit valid[$];
  rand bit data[$];
  
  constraint vld_data_size {
    valid.size() inside {[5:10]};
    data.size() == valid.size();
  }
endclass

module test;
  valid_data_detect datavld;
  initial repeat (3) begin
    datavld=new();
    assert(datavld.randomize()) ;
    foreach(datavld.data[i])
      $display("Before Valid=%0d, Data=%0d", datavld.valid[i], datavld.data[i]);
    datavld.data = datavld.data.find() with (datavld.valid[item.index] ==1);
    foreach(datavld.data[i])
      $display("After Data=%0d", datavld.data[i]);
  end
endmodule
3

Thanks Dave! Just wanted to know a solution without index manipulation and this works.