Randomize with conditional based on non-class signal

SystemVerilog
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1

I’m trying to randomize something like

class upper_config extends uvm_object;

   bit is_special;

   if(!(lower_config.randomize() with { if (is_special) { lower_config_val == 3; } } ) `uvm_fatal(...)
   ...
endclass

Is it allowed to use the signal is_special as part of the conditional to randomize the class lower_config? In simulation it seems to just ignore the conditional, with no failure on randomize().

Edited – bit is_special is not rand.

2

In reply to jlivermore:

It will ignore the constraint if is_special is not set to 1. It doesn’t matter if is_special is declared rand or not because you are not randomizing upper_config. You probably need to show some more code.

3

In reply to dave_59:

The actual code is more complex, so I was trying to simplify my example. Let’s say at the test level we set is_special = 1, then run a function that calls the randomization. I just wanted to make sure I wasn’t violating some language rule. There is probably something going on in my layers of complexity that I have to hunt down. A simple example passed in Questa.