Why associative array will not randomized, if its index is user defined?

SystemVerilog
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1

// Here, I used the user-defined index of an associative array, having enum as data-type…Now I want to randomize this array with 2 constraints…
constraint 1: is each element should be greater than 4
constraint 2: is an array that has only 3 elements…

BUT I GOT BELOW ERROR
I also mentioned the code below…
Kindly help me…

Error:

run -all
# ** Error: Assertion error.
#    Time: 0 ns  Scope: asso_ary_1 File: Assosiative_array_random_elements.sv Line: 27
# asso_ary_size=          0
# asso_ary='{ }

code:

module asso_ary_1;

typedef enum { RED,GREEN, YELLOW } color_t;

class asso_ary_1;

rand bit[7:0] asso_colors [color_t] ;
int i;

constraint c1 { foreach (asso_colors[i]) asso_colors[i] > 4; }
constraint c2 { asso_colors.num() == 3; }


function display();
$display("asso_ary_size=%d", asso_colors.size() );
$display("asso_ary=%p", asso_colors);
endfunction

endclass

asso_ary_1   h1=new;

initial 
begin
     repeat(3)
     begin
         assert( h1.randomize() );
         h1.display();
	 end
end

endmodule
2

In reply to Brinda:
SystemVerilog cannot change the number of elements in an associative array using a constraint. You must allocate elements before calling randomize() or in pre_randomize().