Topics tagged clock

Topic	Replies	Views	Activity
System Verilog Clock Generation SystemVerilog SystemVerilog , constraint , clock	1	154	December 5, 2024
Signal delay by X clock cycles in System Verilog SystemVerilog SystemVerilog , Verilog , Delay , clock , signal	5	24452	December 9, 2022
Clock generation through UVC UVM UVM , uvc , clock	15	8858	March 9, 2022
Clock Monitoring UVM UVM , reference-model , monitor , clock	7	1628	September 3, 2021
Asynchronous state machine with active negative edge SystemVerilog SystemVerilog , clock , State-machine-coverage	1	779	July 29, 2021
Checking 60% duty cycle clock SystemVerilog SystemVerilog , assertion , clock , clock-frequency	5	7979	March 16, 2021
Clock precision setting SystemVerilog SystemVerilog , clock	9	2064	March 6, 2021
SVA to check clock toggling for a fixed number of cycles SystemVerilog SystemVerilog , assertion , SVA , clock , Assertion-Multiple-clocks	4	1761	January 23, 2021
Clock cycles SystemVerilog SystemVerilog , clock	1	823	December 28, 2020
Write a Verilog code and test bench to generate Clock signal of frequency 'f ' and duty cycle 'd ' as per the requirement using only NAND gates SystemVerilog SystemVerilog , clock , clockgeneraation , Clock-Generation , system-verilog-clock	1	1516	December 13, 2020
SV Generate SystemVerilog SystemVerilog , generate , clock , Assign-Delay	1	1249	July 24, 2020
Output to a Text file SystemVerilog SystemVerilog , clock , filewrite	2	4163	June 4, 2020
Advance time in uvm_driver UVM UVM , driver , clock , data-flow-synchronization	5	1310	May 21, 2020
Synchronization: Setting and Clearing a Value using Different Clocks/Processes SystemVerilog SystemVerilog , CDC , clock , Synchronization	5	1616	January 31, 2020
Beginner learning to make a Counter SystemVerilog SystemVerilog , clock , counter-example	4	1870	January 17, 2019
Clk enable UVM UVM , clock , uvm_fatal	1	1721	October 9, 2018
Assertion triggers on edge despite delay added UVM UVM , assertion , Delay , clock	4	1614	March 24, 2018
Clock period absolute time SystemVerilog SystemVerilog , timeunit , clock , Timescale-issue , Period	6	2930	June 11, 2017
Blocking assignment for clock divider SystemVerilog SystemVerilog , clock	5	4592	March 24, 2017
Constraints based on posedge clock SystemVerilog SystemVerilog , Constraint-random-verification , randomization , clock	1	1581	June 14, 2016
How to pass clock to agent if interface does not have it UVM UVM , clock , Generic-clock-generation	2	1619	March 19, 2016
Randomization on clock edge SystemVerilog SystemVerilog , constraint-randomization , dist , clock	3	2164	December 18, 2015
How can I apply word clock jitter in UVM? UVM UVM , clock	1	1686	December 2, 2015
How to model a bus behavior with enable signal in testbench SystemVerilog SystemVerilog , Race-condition , clocking-block-event , clock , Event-Regions	3	2241	September 14, 2015

System Verilog Clock Generation

SystemVerilog

SystemVerilog , constraint , clock

1

154

December 5, 2024

Signal delay by X clock cycles in System Verilog

SystemVerilog

SystemVerilog , Verilog , Delay , clock , signal

5

24452

December 9, 2022

Clock generation through UVC

UVM

UVM , uvc , clock

15

8858

March 9, 2022

Clock Monitoring

UVM

UVM , reference-model , monitor , clock

7

1628

September 3, 2021

Asynchronous state machine with active negative edge

SystemVerilog

SystemVerilog , clock , State-machine-coverage

1

779

July 29, 2021

Checking 60% duty cycle clock

SystemVerilog

SystemVerilog , assertion , clock , clock-frequency

5

7979

March 16, 2021

Clock precision setting

SystemVerilog

SystemVerilog , clock

9

2064

March 6, 2021

SVA to check clock toggling for a fixed number of cycles

SystemVerilog

SystemVerilog , assertion , SVA , clock , Assertion-Multiple-clocks

4

1761

January 23, 2021

Clock cycles

SystemVerilog

SystemVerilog , clock

1

823

December 28, 2020

Write a Verilog code and test bench to generate Clock signal of frequency 'f ' and duty cycle 'd ' as per the requirement using only NAND gates

SystemVerilog

SystemVerilog , clock , clockgeneraation , Clock-Generation , system-verilog-clock

1

1516

December 13, 2020

SV Generate

SystemVerilog

SystemVerilog , generate , clock , Assign-Delay

1

1249

July 24, 2020

Output to a Text file

SystemVerilog

SystemVerilog , clock , filewrite

2

4163

June 4, 2020

Advance time in uvm_driver

UVM

UVM , driver , clock , data-flow-synchronization

5

1310

May 21, 2020

Synchronization: Setting and Clearing a Value using Different Clocks/Processes

SystemVerilog

SystemVerilog , CDC , clock , Synchronization

5

1616

January 31, 2020

Beginner learning to make a Counter

SystemVerilog

SystemVerilog , clock , counter-example

4

1870

January 17, 2019

Clk enable

UVM

UVM , clock , uvm_fatal

1

1721

October 9, 2018

Assertion triggers on edge despite delay added

UVM

UVM , assertion , Delay , clock

4

1614

March 24, 2018

Clock period absolute time

SystemVerilog

SystemVerilog , timeunit , clock , Timescale-issue , Period

6

2930

June 11, 2017

Blocking assignment for clock divider

SystemVerilog

SystemVerilog , clock

5

4592

March 24, 2017

Constraints based on posedge clock

SystemVerilog

SystemVerilog , Constraint-random-verification , randomization , clock

1

1581

June 14, 2016

How to pass clock to agent if interface does not have it

UVM

UVM , clock , Generic-clock-generation

2

1619

March 19, 2016

Randomization on clock edge

SystemVerilog

SystemVerilog , constraint-randomization , dist , clock

3

2164

December 18, 2015

How can I apply word clock jitter in UVM?

UVM

UVM , clock

1

1686

December 2, 2015

How to model a bus behavior with enable signal in testbench

SystemVerilog

SystemVerilog , Race-condition , clocking-block-event , clock , Event-Regions

3

2241

September 14, 2015