Topics tagged clock

Topic	Replies	Views	Activity
Signal delay by X clock cycles in System Verilog SystemVerilog SystemVerilog , Verilog , Delay , clock , signal	5	23663	December 9, 2022
Clock generation through UVC UVM UVM , uvc , clock	15	8386	March 9, 2022
Clock Monitoring UVM UVM , reference-model , monitor , clock	7	1380	September 3, 2021
Asynchronous state machine with active negative edge SystemVerilog SystemVerilog , clock , State-machine-coverage	1	681	July 29, 2021
Checking 60% duty cycle clock SystemVerilog SystemVerilog , assertion , clock , clock-frequency	5	7080	March 16, 2021
Clock precision setting SystemVerilog SystemVerilog , clock	9	1750	March 6, 2021
SVA to check clock toggling for a fixed number of cycles SystemVerilog SystemVerilog , assertion , SVA , clock , Assertion-Multiple-clocks	4	1564	January 23, 2021
Clock cycles SystemVerilog SystemVerilog , clock	1	792	December 28, 2020
Write a Verilog code and test bench to generate Clock signal of frequency 'f ' and duty cycle 'd ' as per the requirement using only NAND gates SystemVerilog SystemVerilog , clock , clockgeneraation , Clock-Generation , system-verilog-clock	1	1386	December 13, 2020
SV Generate SystemVerilog SystemVerilog , generate , clock , Assign-Delay	1	1170	July 24, 2020
Output to a Text file SystemVerilog SystemVerilog , clock , filewrite	2	3713	June 4, 2020
Advance time in uvm_driver UVM UVM , driver , clock , data-flow-synchronization	5	1197	May 21, 2020
Synchronization: Setting and Clearing a Value using Different Clocks/Processes SystemVerilog SystemVerilog , CDC , clock , Synchronization	5	1362	January 31, 2020
Beginner learning to make a Counter SystemVerilog SystemVerilog , clock , counter-example	4	1361	January 17, 2019
Clk enable UVM UVM , clock , uvm_fatal	1	1667	October 9, 2018
Assertion triggers on edge despite delay added UVM UVM , assertion , Delay , clock	4	1533	March 24, 2018
Clock period absolute time SystemVerilog SystemVerilog , timeunit , clock , Timescale-issue , Period	6	2758	June 11, 2017
Blocking assignment for clock divider SystemVerilog SystemVerilog , clock	5	4245	March 24, 2017
Constraints based on posedge clock SystemVerilog SystemVerilog , Constraint-random-verification , randomization , clock	1	1529	June 14, 2016
How to pass clock to agent if interface does not have it UVM UVM , clock , Generic-clock-generation	2	1555	March 19, 2016
Randomization on clock edge SystemVerilog SystemVerilog , constraint-randomization , dist , clock	3	2058	December 18, 2015
How can I apply word clock jitter in UVM? UVM UVM , clock	1	1585	December 2, 2015
How to model a bus behavior with enable signal in testbench SystemVerilog SystemVerilog , Race-condition , clocking-block-event , clock , Event-Regions	3	2131	September 14, 2015