Beginner learning to make a Counter

SystemVerilog
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1

Hi All,

I am teaching myself SystemVerilog and starting with a simple module and hope to add to it as a way to learn this program. I’m trying to make an LED blink for 0.5 secs (I just randomly chose this). For some reason, my LED (named state) stays OFF. Why is it always OFF?

***** FYI: I was told to make the Counter and the State (different from my LED called “state”) in separate always blocks so that I can have a better understanding of how they work in parallel.*****

Here is the code I have so far and I’m not sure what else to try changing. I put comments in so you understand my reasoning. Any input is much appreciated! Thank you!


module Blink
(
input logic Clock_50,           //I'm using a 50MHz clock --> T = 20ns
output logic state = 1'b0       //LED state starts in OFF position
);

//Define counter
logic [24:0] counter = 25'b0;         //25 counters that hold 25 bits that are currently set 
                                      //to zero? Right?
//Create counter: 
always_ff @ (posedge Clock_50)                  //at every pos clk edgd
   begin                                        //begin counting
     counter[24:0] <= counter[24:0] + 25'b1;    //cnt = cnt + 1 (started counting)      
     if (counter[24:0] == 25'd25000000)         //if counter = 25,000,000 (the cycles needed 
        begin                                      //for a 0.5 sec blink)
           counter[24:0] <= 25'0;               //reset counter to zero
        end
     else
        counter[24:0] <= counter[24:0] + 25'b1;  //else, keep counting
   end

//Create State: 
always_ff @ (posedge Clock_50)         //change at positive clk edge
   begin
      if (counter[24:0] == 25'd25000000)    //counter reaches 25,000,000
         begin 
            state <= 1'b1;                  //state is ON (it's connected to an LED)
         end
      else
         state <= 1'b0;                    //state is OFF (it is ALWAYS OFF... \_o_/ ???????)
   end                                                                           
endmodule
2

In reply to gainesy:

How do you know state is always 0? Are you looking at simulation waveforms, or looking at an LED light? In Simulation, can you see the values of the counter changing?

3

In reply to dave_59:

I’m looking at the LED i set on the FPGA starter board. I’ll look into Simulation when I get a chance, I haven’t used that yet.

4

In reply to gainesy:

state is going high for only one clock cycle when counter equals 25000000 and then immediately goes low. You should be inverting the state bit.


always_ff @ (posedge Clock_50)        
   begin
      if (counter == 25'd25000000)  
         begin                 
            state <= ~state;             
         end
   end
5

In reply to sbellock:

Awesome, thank you! That makes sense now.