Beginner learning to make a Counter

SystemVerilog
, ,
4

In reply to gainesy:

state is going high for only one clock cycle when counter equals 25000000 and then immediately goes low. You should be inverting the state bit.


always_ff @ (posedge Clock_50)        
   begin
      if (counter == 25'd25000000)  
         begin                 
            state <= ~state;             
         end
   end