Topics tagged monitor

Topic	Replies	Views	Activity
Monitor Sampling edge UVM SystemVerilog , UVM , UVM-monitor , monitor , driver-monitor , systemverilog-uvm , systemverilog-driver-monitor-virtual-interface-transaction	1	64	January 27, 2025
How to connect scoreboard with more than one monitor UVM UVM , monitor , UVM-scoreboard	6	11196	July 10, 2024
Using $monitor within for loop SystemVerilog SystemVerilog , monitor	2	253	March 26, 2024
Doubt regarding to Monitor transaction collection UVM UVM , UVM-monitor , monitor	1	222	January 4, 2024
Usage of $monitor to print initial value till final value SystemVerilog SystemVerilog , monitor	3	618	October 3, 2023
UVM uses 2 monitors, 1 for input, and 1 for output? UVM SystemVerilog , UVM , monitor	4	571	July 27, 2023
The transaction from the reference model has one positive edge delay to be disaplyed in the scoreboard UVM UVM , reference-model , monitor , UVM-scoreboard	1	514	February 27, 2023
Avoid race condition between two monitors generating dependent transactions SystemVerilog SystemVerilog , Race-condition , monitor	4	905	March 7, 2022
Race condition between write() in UVM scoreboard UVM UVM , monitor , UVM-scoreboard	9	2094	November 26, 2021
My UVM testbench is stuck at monitor UVM UVM , monitor , UVM-Driver	2	1047	November 7, 2021
Clock Monitoring UVM UVM , reference-model , monitor , clock	7	1575	September 3, 2021
$monitor SystemVerilog SystemVerilog , monitor	1	796	May 29, 2021
Pipelined Monitor strategy UVM UVM , monitor , Pipelined	4	2908	November 26, 2020
Prioritize write function call from UVM monitor UVM SystemVerilog , UVM , monitor , UVM-scoreboard	1	1047	August 6, 2020
Monitor blocked SystemVerilog SystemVerilog , monitor	2	760	April 30, 2020
Interface Connection UVM UVM , interface , monitor , activepassive-agent-configuration	3	985	April 25, 2020
Why do we need monitor class? UVM UVM , monitor , passiveagent	1	847	March 31, 2020
Data not getting received in monitor from interface UVM UVM , monitor , data_on_interface	4	1375	November 27, 2019
Driver and monitor implementation UVM UVM , monitor	6	1892	February 22, 2018
Final_block SystemVerilog SystemVerilog , display , monitor , final_block , initial_block	1	1486	January 30, 2018
Forked process behaves differently with/without delay in the process. Without delay simulation is halting otherwise it is smooth (Checker vs Monitor Queue) SystemVerilog SystemVerilog , monitor , Checkers , fork-join_any	3	1582	October 15, 2017
Printing the whole Queue with $monitor SystemVerilog SystemVerilog , queue , monitor	4	2456	September 19, 2016
What is Performance Monitor? UVM UVM , monitor , performance	2	2615	August 24, 2016
Same interface, different monitors UVM UVM , interface , multiple-interface , monitor , multiple-agents	1	1599	October 28, 2015
Where to put checkers? In Monitor or in Scoreboard? UVM UVM , scoreboard , monitor , Checkers	1	5543	June 30, 2015
$monitor is not printing the all value changes when class variable is used inside the system task SystemVerilog SystemVerilog , monitor	6	4091	May 28, 2014

Monitor Sampling edge

SystemVerilog , UVM , UVM-monitor , monitor , driver-monitor , systemverilog-uvm , systemverilog-driver-monitor-virtual-interface-transaction

1

64

January 27, 2025

How to connect scoreboard with more than one monitor

UVM

UVM , monitor , UVM-scoreboard

6

11196

July 10, 2024

Using $monitor within for loop

SystemVerilog

SystemVerilog , monitor

2

253

March 26, 2024

Doubt regarding to Monitor transaction collection

UVM

UVM , UVM-monitor , monitor

1

222

January 4, 2024

Usage of $monitor to print initial value till final value

SystemVerilog

SystemVerilog , monitor

3

618

October 3, 2023

UVM uses 2 monitors, 1 for input, and 1 for output?

UVM

SystemVerilog , UVM , monitor

4

571

July 27, 2023

The transaction from the reference model has one positive edge delay to be disaplyed in the scoreboard

UVM

UVM , reference-model , monitor , UVM-scoreboard

1

514

February 27, 2023

Avoid race condition between two monitors generating dependent transactions

SystemVerilog

SystemVerilog , Race-condition , monitor

4

905

March 7, 2022

Race condition between write() in UVM scoreboard

UVM

UVM , monitor , UVM-scoreboard

9

2094

November 26, 2021

My UVM testbench is stuck at monitor

UVM

UVM , monitor , UVM-Driver

2

1047

November 7, 2021

Clock Monitoring

UVM

UVM , reference-model , monitor , clock

7

1575

September 3, 2021

$monitor

SystemVerilog

SystemVerilog , monitor

1

796

May 29, 2021

Pipelined Monitor strategy

UVM

UVM , monitor , Pipelined

4

2908

November 26, 2020

Prioritize write function call from UVM monitor

UVM

SystemVerilog , UVM , monitor , UVM-scoreboard

1

1047

August 6, 2020

Monitor blocked

SystemVerilog

SystemVerilog , monitor

2

760

April 30, 2020

Interface Connection

UVM

UVM , interface , monitor , activepassive-agent-configuration

3

985

April 25, 2020

Why do we need monitor class?

UVM

UVM , monitor , passiveagent

1

847

March 31, 2020

Data not getting received in monitor from interface

UVM

UVM , monitor , data_on_interface

4

1375

November 27, 2019

Driver and monitor implementation

UVM

UVM , monitor

6

1892

February 22, 2018

Final_block

SystemVerilog

SystemVerilog , display , monitor , final_block , initial_block

1

1486

January 30, 2018

Forked process behaves differently with/without delay in the process. Without delay simulation is halting otherwise it is smooth (Checker vs Monitor Queue)

SystemVerilog

SystemVerilog , monitor , Checkers , fork-join_any

3

1582

October 15, 2017

Printing the whole Queue with $monitor

SystemVerilog

SystemVerilog , queue , monitor

4

2456

September 19, 2016

What is Performance Monitor?

UVM

UVM , monitor , performance

2

2615

August 24, 2016

Same interface, different monitors

UVM

UVM , interface , multiple-interface , monitor , multiple-agents

1

1599

October 28, 2015

Where to put checkers? In Monitor or in Scoreboard?

UVM

UVM , scoreboard , monitor , Checkers

1

5543

June 30, 2015

$monitor is not printing the all value changes when class variable is used inside the system task

SystemVerilog

SystemVerilog , monitor

6

4091

May 28, 2014