Topics tagged monitor

Topic	Replies	Views	Activity
Monitor Sampling edge UVM SystemVerilog , UVM , UVM-monitor , monitor , driver-monitor , systemverilog-uvm , systemverilog-driver-monitor-virtual-interface-transaction	1	103	January 27, 2025
How to connect scoreboard with more than one monitor UVM UVM , monitor , UVM-scoreboard	6	11619	July 10, 2024
Using $monitor within for loop SystemVerilog SystemVerilog , monitor	2	270	March 26, 2024
Doubt regarding to Monitor transaction collection UVM UVM , UVM-monitor , monitor	1	231	January 4, 2024
Usage of $monitor to print initial value till final value SystemVerilog SystemVerilog , monitor	3	721	October 3, 2023
UVM uses 2 monitors, 1 for input, and 1 for output? UVM SystemVerilog , UVM , monitor	4	605	July 27, 2023
The transaction from the reference model has one positive edge delay to be disaplyed in the scoreboard UVM UVM , reference-model , monitor , UVM-scoreboard	1	530	February 27, 2023
Avoid race condition between two monitors generating dependent transactions SystemVerilog SystemVerilog , Race-condition , monitor	4	919	March 7, 2022
Race condition between write() in UVM scoreboard UVM UVM , monitor , UVM-scoreboard	9	2154	November 26, 2021
My UVM testbench is stuck at monitor UVM UVM , monitor , UVM-Driver	2	1057	November 7, 2021
Clock Monitoring UVM UVM , reference-model , monitor , clock	7	1625	September 3, 2021
$monitor SystemVerilog SystemVerilog , monitor	1	797	May 29, 2021
Pipelined Monitor strategy UVM UVM , monitor , Pipelined	4	2960	November 26, 2020
Prioritize write function call from UVM monitor UVM SystemVerilog , UVM , monitor , UVM-scoreboard	1	1059	August 6, 2020
Monitor blocked SystemVerilog SystemVerilog , monitor	2	762	April 30, 2020
Interface Connection UVM UVM , interface , monitor , activepassive-agent-configuration	3	1010	April 25, 2020
Why do we need monitor class? UVM UVM , monitor , passiveagent	1	850	March 31, 2020
Data not getting received in monitor from interface UVM UVM , monitor , data_on_interface	4	1384	November 27, 2019
Driver and monitor implementation UVM UVM , monitor	6	1907	February 22, 2018
Final_block SystemVerilog SystemVerilog , display , monitor , final_block , initial_block	1	1498	January 30, 2018
Forked process behaves differently with/without delay in the process. Without delay simulation is halting otherwise it is smooth (Checker vs Monitor Queue) SystemVerilog SystemVerilog , monitor , Checkers , fork-join_any	3	1587	October 15, 2017
Printing the whole Queue with $monitor SystemVerilog SystemVerilog , queue , monitor	4	2487	September 19, 2016
What is Performance Monitor? UVM UVM , monitor , performance	2	2670	August 24, 2016
Same interface, different monitors UVM UVM , interface , multiple-interface , monitor , multiple-agents	1	1605	October 28, 2015
Where to put checkers? In Monitor or in Scoreboard? UVM UVM , scoreboard , monitor , Checkers	1	5621	June 30, 2015
$monitor is not printing the all value changes when class variable is used inside the system task SystemVerilog SystemVerilog , monitor	6	4136	May 28, 2014