How to connect scoreboard with more than one monitor

hi everybody,
In my env class , there is a master agent and slave agent.
and i want to connect master agent monitor and slave agent monitor to scoreboard.

The query i am having is :

  1. do i need to create two scoreboard for connecting two monitors.
  2. and how can i give defination for two write function , one write function for master agent monitor and second write for slave agent monitor .

Please help me for the above question.

1 Like

In reply to Manirama:

I think you not need to create two scoreboard.

You can follow below steps.

  1. declare analysis port inside Master agent monitor.

uvm_analysis_port #(seq_item) master_mon2scb;

  1. declare analysis port inside Slave agent monitor.

uvm_analysis_port #(seq_item) slave_mon2scb;

3)declare 2 analysis imp to get monitor transaction inside your scoreboard.


`uvm_analysis_imp_decl(_master_mon2scb)
`uvm_analysis_imp_decl(_slave_mon2scb)
......
......
uvm_analysis_imp_master_mon2scb#(seq_item,scb) m_mon2scb;
uvm_analysis_imp_slave_mon2scb#(seq_item,scb) s_mon2scb;
.......
.......
//create both port 
........
........
function write_master_mon2scb( seq_item m_tr );
.....
endfunction

function write_slave_mon2scb( seq_item s_tr );
.....
endfunction

  1. connect inside connect phase of your environment.

m_agent.mon.master_mon2scb.connect(env.scb.m_mon2scb);
s_agent.mon.slave_mon2scb.connect(env.scb.s_mon2scb);

I hope it helps.

Thanks,
Harsh

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In reply to Manirama:

hi everybody,
In my env class , there is a master agent and slave agent.
and i want to connect master agent monitor and slave agent monitor to scoreboard.
The query i am having is :

  1. do i need to create two scoreboard for connecting two monitors.
  2. and how can i give defination for two write function , one write function for master agent monitor and second write for slave agent monitor .
    Please help me for the above question.

You did not explain what you want to compare and a few other details of your UVM environment, like the seq_items do you have a master and a seperate slave seq_item?

See the Advanced UVM video course: How TLM Works or the UVM Cookbook for how to do this.

In reply to harsh pandya:

If we need to connect 8 monitors to single scoreboard ,then 8 write() functions need to implement in scoreboard class ,Any other way to optimize instead of writing 8 write() functions ??

In reply to dddvlsique:

As shown in Advaned UVM/How TLM Works, there are two ways to do this. The problem is that the write() call from an analysis_port supports 1:many calls, but not many:1 calls. So, while a single monitor can be connected to multiple scoreboards, the only way to connect a single scoreboard to multiple monitors is to have multiple analysis_exports(/imps) in your scoreboard.

The first method, as you surmised, is to create multiple implementations of write() in the scoreboard using the `uvm_analysis_imp_decl() macro.


`uvm_analysis_imp_decl(_BEFORE)
`uvm_analysis_imp_decl(_AFTER)
class score extends uvm_component;
  `uvm_component_utils(score);
  uvm_analysis_imp_BEFORE #(tr, score) before_export;
  uvm_analysis_imp_AFTER #(tr, score) after_export;
  virtual function void write_BEFORE(tr);
    …
  endfunction
  virtual function void write_AFTER(tr);
    …
  endfunction
endclass

The other alternative is to use uvm_tlm_analysis_fifos to provide the exports and therefore the write methods:


class score2 extends uvm_component;
  `uvm_component_utils(score2);
  uvm_analysis_export #(tr) b4_export;
  uvm_analysis_export #(tr) after_export;
  uvm_tlm_analysis_fifo #(tr) b4_fifo,after_fifo;
  function void connect_phase( uvm_phase phase );
    b4_export.connect(b4_fifo.analysis_export);
    after_export.connect(after_fifo.analysis_export);
  endfunction
  task run_phase(uvm_phase phase);
    b4_fifo.get(t1);
    after_fifo.get(t2);
…
endclass

Note that in this second case, you need a run_phase() method to actively pull the data from the fifos.

i Tried the first method but it’s not working as mentioned.

link of the code : Edit code - EDA Playground

please help to find what I am mess it up with .

class sender extends uvm_component;

`uvm_component_utils(sender)

uvm_analysis_port#(int) send_port;

function new(string name=“sender”,uvm_component parent);
super.new(name,parent);
send_port=new(“send_port”,this);
endfunction

task run_phase(uvm_phase phase);
phase.raise_objection(this);
send_port.write(10);
send_port.write_BEFORE(34);
$display(“send the value from run_Phase”);
phase.drop_objection(this);
endtask

endclass

class receiver extends uvm_component;

`uvm_component_utils(receiver)

`uvm_analysis_imp_decl(_BEFORE)

uvm_analysis_imp#(int,receiver) rsv_port;
uvm_analysis_imp_BEFORE#(receiver) before_export;

function new(string name=“receiver”,uvm_component parent);
super.new(name,parent);
rsv_port=new(“rsv_port”,this);
before_export=new(“before_export”,this);
endfunction

function void write(int a);
$display(“value of a received=%0d”,a);
endfunction

function void write_BEFORE(int a);
$display(“value of a received=%0d”,a);
endfunction
endclass

class env extends uvm_env;

`uvm_component_utils(env)

sender sen;
receiver rsv;

function new(string name=“env”,uvm_component parent);
super.new(name,parent);
endfunction

function void build_phase(uvm_phase phase);
super.build_phase(phase);
sen=sender::type_id::create(“sen”,this);
rsv=receiver::type_id::create(“rsv”,this);
endfunction

function void connect_phase(uvm_phase phase);
sen.send_port.connect(rsv.rsv_port);
sen.send_port.connect(rsv.before_export);
endfunction

endclass

module top;

initial
run_test(“env”);
endmodule

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