Topics tagged driver-monitor

Topic	Replies	Views	Activity
Send a value from driver to monitor without using TLMs UVM UVM , driver-monitor	8	1475	July 27, 2020
Write a monitor code for 5 stage pipeline in which if in 1st clk valid signal is high then in 2nd cycle signal1 goes high and in 3rd cycle signal 2 goes high and so on signal 3 and signal 4 UVM UVM , driver-monitor	3	1213	February 16, 2019
What is the difference between the two code snippets? SystemVerilog SystemVerilog , posedge-clk , posedge-clk-begin , driver-monitor	6	2858	October 11, 2017
I2C SCL generation for single master UVM UVM , driver-monitor , I2C	4	5163	November 23, 2016
Ways to make calls of two tasks to execute concurrently? SystemVerilog SystemVerilog , sv-env , driver-monitor	4	6645	August 25, 2015
Difference between drive and monitor in system verilog SystemVerilog SystemVerilog , System-Verilog , driver-monitor	1	2921	July 26, 2015