What is the difference between the two code snippets?

SystemVerilog
, , ,
1

What is the difference between:


forever begin
   @posedge(clk) begin
      if(vif.sof == 1) begin 
         //some code here
      end
   end
end


forever begin
   @posedge(clk);
   if(vif.sof == 1) begin
      //some code here
   end
end

Does the begin…end that goes with @(posedge clk) make a difference ?

2

In reply to Verif Engg:
event_controls like @ and # in procedural code are not statement by themselves; they are prefixes to the statements that follow. And a statement can be a simple statement, like an assignment, or a block like begin/end or fork/join. And a block is allowed wherever a single statement is allowed.

When you write @(posedge clk); it is really @(posedge clk) null_statement;

I should have given you enough information to answer your question, but here is another variation:

forever 
        @posedge(clk)
        if(vif.sof == 1) begin
           //some code here
        end

Now there is a big difference if a semicolon follows @(posedge clk) or not.

3

In reply to dave_59:

Thanks Dave for the response but honestly it added to my confusion :(

I thought, the below two are the same !


forever  begin
   @posedge(clk)
   if(vif.sof == 1) begin
      //some code here
   end
end 


forever begin
   @posedge(clk);
   if(vif.sof == 1) begin
      //some code here
   end
end

Would really appreciate it if you could explain the difference. Thanks!

4

In reply to Verif Engg:

They there is no functional difference in the last two examples you wrote. But that is not the same as

forever 
        @posedge(clk) ; // adding semicolon here is not the same 
        if(vif.sof == 1) begin
           //some code here
        end
5

In reply to Verif Engg:

If I may suggest - please run both code in 2 different simulations and observe (Make sure clock is ticking, vif.sof is set to 1 and 0 during the sims).

Be ready for a good learning experience :-)

Regards
Srini

6

In reply to Srini @ CVCblr.com:

ok, I coded up something simpler to help me understand and so far my learning experience has been that I see no difference. I have cut and paste the code here; If either of you can look thru the code and help me understand the concept, that would be great.

TRAIL 1 - 1st simulation, with semicolon
TRIAL 2 - 2nd simulation, no semicolon


module TB;
  
  bit clk;
  bit flag;
  bit another_flag;
  
  initial begin
    forever #5 clk = ~clk;
  end
  
  
  initial begin
    forever begin
      @(posedge clk)
      flag = 1;
      @(negedge clk)
      flag = 0;
      
    end  
  end
  
  
  //TRIAL 1
  initial begin
    @(posedge clk);
    if(flag) begin
      $display("I am here ");
      another_flag = 1;
    end  
    else 
      another_flag = 0;
  end
  
/*  
  
  //TRIAL 2
  initial begin
    @(posedge clk) //NOTE that semi-colon is missing here
    if(flag) begin
      $display("I am here ");
      another_flag = 1;
    end  
    else 
      another_flag = 0;
  end
  
*/

 initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, TB);
    #1us;
    $finish;
  end
  
  
endmodule
7

In reply to Verif Engg:

Where’s the forever loop in your trial code? Try the code I posted with the only difference being the semicolon.

You are mixing and confusing two independent concepts:

  1. how begin/end creates a sequential set of statements that can be used as a single statement.
  2. how event controls can be used to modify the timing of a single statement.

Maybe it might help to ask what difference do you think there might be in the code from original question you asked?