What is the difference between the two code snippets?

SystemVerilog
, , ,
6

In reply to Srini @ CVCblr.com:

ok, I coded up something simpler to help me understand and so far my learning experience has been that I see no difference. I have cut and paste the code here; If either of you can look thru the code and help me understand the concept, that would be great.

TRAIL 1 - 1st simulation, with semicolon
TRIAL 2 - 2nd simulation, no semicolon


module TB;
  
  bit clk;
  bit flag;
  bit another_flag;
  
  initial begin
    forever #5 clk = ~clk;
  end
  
  
  initial begin
    forever begin
      @(posedge clk)
      flag = 1;
      @(negedge clk)
      flag = 0;
      
    end  
  end
  
  
  //TRIAL 1
  initial begin
    @(posedge clk);
    if(flag) begin
      $display("I am here ");
      another_flag = 1;
    end  
    else 
      another_flag = 0;
  end
  
/*  
  
  //TRIAL 2
  initial begin
    @(posedge clk) //NOTE that semi-colon is missing here
    if(flag) begin
      $display("I am here ");
      another_flag = 1;
    end  
    else 
      another_flag = 0;
  end
  
*/

 initial begin
    $dumpfile("dump.vcd");
    $dumpvars(0, TB);
    #1us;
    $finish;
  end
  
  
endmodule