What is the difference between the two code snippets?

SystemVerilog
, , ,
3

In reply to dave_59:

Thanks Dave for the response but honestly it added to my confusion :(

I thought, the below two are the same !


forever  begin
   @posedge(clk)
   if(vif.sof == 1) begin
      //some code here
   end
end 


forever begin
   @posedge(clk);
   if(vif.sof == 1) begin
      //some code here
   end
end

Would really appreciate it if you could explain the difference. Thanks!