Monitor Sampling edge

UVM
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1

Hi all,

I am using cycle based simulator like Verilator for my test setup and I am driving my dut signals on the posedge of the clock , but when in monitor class when I sample data on the posedge of the clock I am unable to retrieve the values (through waveforms I can sense that they are updated on that particular edge)

So I wanna use negedge in the monitor class to sample the updated values from signals

in driver | in monitor
always @posedge clk | always @negedge clk
//drive signals to dut | // sample signals from dut

Is this the right approach for this delay issue, or is there a standard approach for this race-around condition?

Thank you.

2

You use the same approach the DUT uses between modules in the design as you would between the DUT and testbench. You can use non-blocking assignments, or different clock edges.