systemverilog-driver-monitor-virtual-interface-transaction
| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| Monitor Sampling edge |
|
1 | 110 | January 27, 2025 |
| What is virtual interface. why the virtual interface is used in systemverilog, what is the difference between a normal interface and a virtual interface |
|
1 | 601 | July 27, 2023 |
| In which phase of simulation virtual interface will assign the value of actual interface |
|
1 | 337 | July 13, 2023 |
| VERIFICATION ASYNCHRONOUS FIFO CUMMINGS |
|
10 | 2722 | February 1, 2023 |
| Driving internal signal of DUT from uvm driver |
|
1 | 642 | August 19, 2022 |
| Virtual interface for internal signals |
|
3 | 2064 | February 14, 2022 |
| [SystemVerilog] Difference between `wait(cb.signal == 1'b1)` and `@(cb iff cb.signal == 1'b1)` |
|
5 | 3317 | October 1, 2021 |
| For Dpram . how i can write a constraint block using both random write and random read signals such that write should come first and later read signal |
|
5 | 1692 | August 19, 2020 |