In which phase of simulation virtual interface will assign the value of actual interface

I have a question about assigning the actual interface to virtual interface.
we have 3 phases of simulation : 1.compilation 2.elobration 3.runtime
all static property get its values in elaboration time.
so I have a question when the virtual interface gets its memory??runtime or elaboration time??
In UVM we set the virtual interface value through config_db get method which is static so…
virtual interface should get the values as elaboration type??
please correct me if I am wrong…

In reply to kamal_here:

Your assumptions are incorrect.

Static variables get initialized once at time 0 during runtime, but before any initial or always processes have started. You can make procedural assignments to static variables anytime later in runtime.

Static methods like uvm_config_db::set() can get called any point during runtime. Static methods cannot access non-static members of its class without a reference to an object handle. Typically,
uvm_config_db::set()
gets called as part of an initial process, and that call makes assignments to static properties within the uvm_config_db class.

Parameter values and types are what get resolved during elaboration.

You might want to read The life of a SystemVerilog variable