clock-synchronous
| Topic | Replies | Views | Activity | |
|---|---|---|---|---|
| [SystemVerilog] Difference between `wait(cb.signal == 1'b1)` and `@(cb iff cb.signal == 1'b1)` |
|
5 | 3381 | October 1, 2021 |
| How to code interface of an agent in which the sequence item signals could be synchronous or asynchronous? |
|
1 | 1211 | May 15, 2020 |
| Event scheduling - evaluation time stamp |
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1 | 776 | February 3, 2020 |