Topics tagged clock-synchronous

Topic	Replies	Views	Activity
[SystemVerilog] Difference between `wait(cb.signal == 1'b1)` and `@(cb iff cb.signal == 1'b1)` SystemVerilog SystemVerilog , Clocking-Block , wait-statement , clock-synchronous , systemverilog-driver-monitor-virtual-interface-transaction	5	3016	October 1, 2021
How to code interface of an agent in which the sequence item signals could be synchronous or asynchronous? UVM UVM , interface , asynchronous , clock-synchronous	1	1187	May 15, 2020
Event scheduling - evaluation time stamp SystemVerilog SystemVerilog , verilog-blocking-assignments , systemverilog-scheduling , events-region , clock-synchronous	1	759	February 3, 2020