clock-synchronous
Topic | Replies | Views | Activity | |
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[SystemVerilog] Difference between `wait(cb.signal == 1'b1)` and `@(cb iff cb.signal == 1'b1)` |
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5 | 2748 | October 1, 2021 |
How to code interface of an agent in which the sequence item signals could be synchronous or asynchronous? |
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1 | 1135 | May 15, 2020 |
Event scheduling - evaluation time stamp |
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1 | 707 | February 3, 2020 |