How to code interface of an agent in which the sequence item signals could be synchronous or asynchronous?

Hi all,

so I’m trying to create a generic agent for GPIO(general purpose input output) signals. So I plan to take user input from environment (in a task called in agent configuration class) and the user will put the fields of sequence item which they want to drive to the driver, and the configuration class will be passed down to rest of the testbench through config db/ resource db.

Some of these could be synchronous fields, and some could be asynchronous. For synchronous, we could have a clocking block in the interface. What if some signals are synchronous and some are asynchronous? How to create a general interface for the same?

P.S. I have added code of interface in case all signals are synchronous:

**interface sideband_if(input logic clk,reset);
define MAX_VAL 15 define BUS_WIDTH 31
//---------------------------------------
//declaring the signals
//---------------------------------------
logic [MAX_VAL:0] interrupt1;
//logic [15:8]interrrupt2;
logic [BUS_WIDTH:MAX_VAL+1] interrupt2; //value 0

//---------------------------------------
//driver clocking block
//---------------------------------------
clocking driver_cb @(posedge clk);
default input #1 output #1;
inout interrupt1;
inout interrupt2;
//inout interrupt3;
endclocking

//---------------------------------------
//driver modport
//---------------------------------------
modport DRIVER (clocking driver_cb,input clk,reset);

endinterface**

In reply to raivaichu1109:

The (SytemVerilog)interface does not differentiate between synchronous (clocked) and asynchronous signals. And on the RT level it does not matter if the signals are synchronous/asynchronous. Even using a clocking block, which is only an option - it does not matter. Because the clocking block is delaying the signals by a defined time and not by clock cycles.