Hi, I’m trying to refactor some legacy code to make it synchronous with the clock and face the below issue.
i expect the rddata_valid_sync(legacy code) and rddata_valid_sync_new(new code) to be identical but i see that rddata_valid_sync_new is delayed by #1 cycle compared to rddata_valid_sync.
Can someone guide me where I’m going wrong? Link to waveform
I can think that rddat_val(input to module1) might still be in transition, in that case how do I make both of them identical because I don’t want to miss the data that’s being sampled.
Any suggestions would be very helpful. Thanks in advance.
// legacy code
// rddat_val is input to module1(that runs on uclk) coming from module2 running also on uclk
// uclk and clk_2 are different but synchronous
fork // level_1
forever begin // thread1
@(posedge vif.clk_2);
fork // level_2
begin
wait (last_rddata_done);
@(negedge vif.clk_2);
vif.rddata_valid_sync = 0;
last_rddata_done = 1'b0;
end
begin
wait ( (rddata_valid == 1'b1) && (last_rddata_done == 1'b0) );
vif.rddata_valid_sync = 1;
@(negedge vif.clk_2);
vif.rddata_valid_sync = 0;
end
join_any
disable fork;
#1;
end
forever begin // thread2
fork // level_2
begin
@ (posedge vif.rddat_val);
rddata_valid = 1'b1;
end
begin
@ (negedge vif.rddat_val);
rddata_valid = 1'b0;
last_rddata_done = 1;
#1;
end
join_any
disable fork;
end
join_any
disable fork; // level_1
// new code
// since rddat_val is signal to module 1 that runs ons on uclk
// i made it synchronous to uclk.
// uclk and clk_2 are different but synchronous
forever begin
@ (posedge vif.uclk iff vif.rddat_val);
vif.rddata_valid_sync_new = 1;
@(negedge vif.uclk);
vif.rddata_valid_sync_new = 0;
end