My UVM testbench is stuck at monitor

UVM
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1

I have developed my testbench and I can run it and everything works fine but for Only first sequence. After That the test runs infinitely can’t execute the other sequences.
I think It’s stuck in wait statement in monitor. But I don’t know why the driver does not start the second sequence. What could be causing that it stops after the second sequence ?

UVM Log:

UVM_INFO …/agent_hl/monitor_hl.sv(30) @ 365: uvm_test_top.env_h.agnt_hl.mn_hl [uvm_test_top.env_h.agnt_hl.mn_hl] Here Again

UVM_INFO …/seq_iteml.sv(56) @ 365: reporter@@item [item.do_compare()] Cast succeded.

UVM_INFO …/scoreboard.sv(32) @ 365: uvm_test_top.env_h.scb [uvm_test_top.env_h.scb] Transaction Passed

Monitor run phase Code:


forever begin
            item = seq_iteml::type_id::create("item"); 
            `uvm_info(get_full_name(),"Here Again", UVM_HIGH)
                     //`uvm_info(get_full_name(),"Here Again", UVM_HIGH)
                     //`uvm_info(get_full_name(),$sformatf("\ndata ready  = 0x%h \n", vif.o_TX_Ready), UVM_HIGH)
                @(posedge vif.i_Clk or negedge vif.i_Clk);
                wait(vif.i_TX_DV == 1) 
                    item.data_in   = vif.i_TX_Byte;
                wait(vif.o_RX_DV == 1); 
                    item.data_out  = vif.o_RX_Byte;

                        
                `uvm_info(get_full_name(),item.convert2string(), UVM_HIGH)
                mhl_analysis_port.write(item);
            

        end

Driver run phase Code:


reset_vals();
        forever begin 

            seq_item_port.get_next_item(item);
            forever begin
                @(posedge vif.i_Clk);
                if(vif.o_TX_Ready) begin
                `uvm_info(get_full_name(),$sformatf("\ndata_in  = 0x%h \n", item.data_in), UVM_HIGH)
                    vif.i_TX_DV <= 1;
                    vif.i_TX_Byte <= item.data_in;
                @(posedge vif.i_Clk);
                break;
            end
      end
      
      //drive();
      seq_item_port.item_done(item);
      vif.i_TX_DV <= 0;

        end
2

In reply to Mostafa Ellebody:

You don’t need two forever blocks in your driver. You should have only one forever block that calls get_next_item() and then drives the transaction. Also, you need to call item_done() when the transaction is complete.

Something like:


  forever begin
    seq_item_port.get_next_item(item);
    @(posedge vif.i_Clk);
    while (vif.o_TX_Ready != 1'b1) @(posedge vif.i_Clk);  // Wait for DUT to be ready
    `uvm_info(get_full_name(),$sformatf("\ndata_in  = 0x%h \n", item.data_in), UVM_HIGH)
    vif.i_TX_DV <= 1;
    vif.i_TX_Byte <= item.data_in;
    @(posedge vif.i_Clk);
    seq_item_port.item_done(item);
  end
3

I have discovered where the problem was. It was in another driver that kept running forever. Sorry for your time.