Using $monitor within for loop

SystemVerilog
,
1

Hi All,
I was trying the following code

module tb;  
  integer i;  
  initial begin    
    for( i = 0 ; i < 4 ; i++) begin
      $monitor("i is %0d",i);
    end  
  end 
endmodule

I observe the output as i is 4
I am aware that in case of multiple $monitor the last one takes precedence.
Since last $monitor executes with value of i as 3 , why is it that we observe 4 instead of 3 ?

2

i has the value 4 as it exits the loop at time 0.

$monitor prints the values of its arguments at the end of a time slot. It sets up a background process printing this in the time slot when the call is first made and then every time an argument changes it value.

3

Thanks Dave.
Since $monitor executes in postponed region and as the value of ‘i’ is 4 by then we observe the same.