Usage of $monitor to print initial value till final value

SystemVerilog
,
1

Hi All,

typedef enum{s0, s1, sx, sz} states;
module m1;
  states sa;
  initial begin
    $monitor("time %0t state %0s", $time, sa.name);
  end
  initial begin
    #sa $cast(sa, sa+0);
    #sa $cast(sa, sa+1);
    #sa $cast(sa, sa+1);
    #sa $cast(sa, sa+1);
  end
endmodule

output

time 0 state s1
time 1 state sx
time 3 state sz

=================
I would like to print all states values using $monitior.
But the initial state value (s0) is not coming.

As we know “$monitor prints the value only if there is a change in the simulation time”
0ns, no change in the simulation, hence its not getting printed I feel.

Is it possible to get all iteration values using $moonitior in someway? or $display is the only solution.
Kindly advice

2

In reply to Mahesh K:

Verilog Display Tasks.

$monitor prints out variable or expression values whenever the variable or expression in its argument list changes.

So, at S0 state, nothing changes so you won’t get it printed unless you change you code as below starting enum with 1 instead of 0 and initialize sa with 0.

typedef enum{s0 = 1, s1, sx, sz} states;
module m1;
states sa;
initial begin
 sa = 'h0;
end
initial begin
$monitor("time %0t state %0s", $time, sa.name);
end
initial begin
#sa $cast(sa, sa+1);
#sa $cast(sa, sa+1);
#sa $cast(sa, sa+1);
#sa $cast(sa, sa+1);
end
endmodule

time 0 state s0
time 1 state s1
time 3 state sx
time 6 state sz
3

In reply to nhp:

nhp, the code is illegal as you cannot assign in numerical value to an enumerated variable.

$monitor only prints once at the end of a time slot when the call is made, and then once at the end of each time slot when an argument changes. So you need more than a zero delay between the first two assignments.

4

In reply to dave_59:

thanks Dave. the simulator let it go with warning that I didn’t realized.

I could get the same results just with initialize the S0 = 1 in the enum and no more warnings.
This is because the delay gets in before the first statement.

typedef enum{s0 = 1, s1 , sx, sz} states;
module m1;
states sa;
initial begin
$monitor(“time %0t state %0s”, $time, sa.name);
end
initial begin
#sa $cast(sa, sa+1);
#sa $cast(sa, sa+1);
#sa $cast(sa, sa+1);
#sa $cast(sa, sa+1);
end
endmodule

time 0 state s0
time 1 state s1
time 3 state sx
time 6 state sz