Usage of $monitor to print initial value till final value

SystemVerilog
,
2

In reply to Mahesh K:

Verilog Display Tasks.

$monitor prints out variable or expression values whenever the variable or expression in its argument list changes.

So, at S0 state, nothing changes so you won’t get it printed unless you change you code as below starting enum with 1 instead of 0 and initialize sa with 0.

typedef enum{s0 = 1, s1, sx, sz} states;
module m1;
states sa;
initial begin
 sa = 'h0;
end
initial begin
$monitor("time %0t state %0s", $time, sa.name);
end
initial begin
#sa $cast(sa, sa+1);
#sa $cast(sa, sa+1);
#sa $cast(sa, sa+1);
#sa $cast(sa, sa+1);
end
endmodule

time 0 state s0
time 1 state s1
time 3 state sx
time 6 state sz