Write a Verilog code and test bench to generate Clock signal of frequency 'f ' and duty cycle 'd ' as per the requirement using only NAND gates

SystemVerilog
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I have tried designing a code and testbench for the above question but my EPWave does not give me the desired output clock signals. I would highly appreciate it if someone could help me out by giving a prompt response.

Please note: I am trying to execute the code in a Cadence Xcelium 20.09 simulator.

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In reply to anon_student:
Clock generators use crystal oscillators cut frequencies that can be cut down to the desired circuit frequency with FFs.

You can make an oscillator out of NAND gates, but the frequency is not stable and depends on the gate delays. That design takes an odd chain of connected inverters, and then tie the output of that chain to the input of that chain. By assuming certain gate delays you can approach the desired frequency.

I would be interested to see your design.
Ben