Constraints based on posedge clock

SystemVerilog
, , ,
1

I am reading through a code written by a colleague, could someone please help me understand what it is supposed to be doing?
I don’t know what the intent of this code is, there are no helpful comments.

bit inject;
forever begin
   @(posedge clk);
   randomize(inject) with { inject dist { 1'b1 := 0,
                                          1'b0 := 100
   };
   if ( inject) 
      <error injection code here>
end

The test is expected to be injecting errors, but it is not. And the root cause lies in this code.

Thanks

2

In reply to Sharandiva:
Whoever wrote this code made two big mistakes. First, they reversed the weight and the expression value positions. The weight should be on the left and the value should be on the right. Second, they used a weight of 0, which is means the value should not be a solution. See 18.5.4 Distribution in the 1800-2012 LRM. They probably meant

randomize(inject) with { inject dist {  1 := 1'b1,
                                       99 := 1'b0
   };

which means inject is true 1 out of 100 times.