Do system Verilog support delays inside. Suppose I am using genvar to generate multiple clocks like below
reg [7:0]clk;
genvar i;
generate
for (i=0; i < 7; i++) begin
#1 clk[i]=~clk[i];
end
endgenerate
I am getting an error: near "#": syntax error, unexpected '#'
.
how can we resolve it, whether can I use delays inside generate block ?