Randomization on clock edge

SystemVerilog
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1

My aim is to randomize a one bit variable on posedge of clock, such that value is 0 for 100 clocks and then 1 for one clock.

This is the code I have:

@(posedge pin_if.clk);
randomize(inject) with {
inject dist { 1’b0 := 100,
1’b1 := 1
};

It doesn’t work as expected, what am I missing here?

2

In reply to Sharandiva:

What you are asking for is not a random distribution at all. You need a non-random counter.

3

In reply to dave_59:

Thanks for your response.
What is the outcome of this piece of code?

4

In reply to Sharandiva:

Remember that each call to randomize() produces results that are independent of the previous call. Just like tossing a coin - you have a 50/50% chance of heads or tails. If you toss it 100 times, it’s not going to alternate heads and tails evenly.

So in your piece of code, if you have 1000 clocks cycles, it will probably choose 1’b1 10 times and 1’b0 990 times.