System Verilog Clock Generation

Write a code to generate the clock with a random duty cycle between 10% to 80% for each clock cycle, the clock period should be same for each cycle and the clock period should parametrized.

Untested
https://www.perplexity.ai/search/write-a-code-to-generate-the-c-etpNhjiGS_KRCqWpRBgPbg