Want to generate array of one hot numbers using system Verilog constraints

SystemVerilog
,
1

I want to generate 9 one hot numbers each with 9 bit length in system Verilog constraints . But the below code is generating all 0s. Any idea whats going wrong?


class unique_elements;
  rand bit [8:0] my_var[9];
  
  
  constraint my_var_c{
    foreach(my_var[i]) 
    {
      $countones(my_var[i]) == 1;            
    }
      unique{my_var};
  }
      
  function void display();
    foreach(my_var[i])
      $display("my_var = %p",my_var[i]);

  endfunction    
      
      
endclass

program unique_elements_randomization;
  unique_elements pkt;

  initial begin
    pkt = new();
    pkt.randomize();
    pkt.display();   
  end
  
endprogram
2 
class Example;
	rand bit[8:0] num;
	bit[8:0] num_q[$];

	constraint c1 {$countones(num) == 1;}
	constraint c2 {!(num inside {num_q});}

	function void post_randomize();
	  num_q.push_back(num);
		$display("num = %b", num);
	endfunction

endclass

module TB;
	Example E;
	initial begin
		E = new();
		repeat(9) begin
			assert(E.randomize());
		end
  end		
endmodule
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3

You have run into a tool specific problem. out of 4 tools on www.edplayground.com give you the desired results.

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