Limit the number of transitions in a 32 bit number

SystemVerilog
, ,
1

If you have a 32 bit value, write a constraint which constrains the number of transitions. Example,10001 has 2 transitions as you parse it. 11010011 has 3 transitions. Can we use the .sum() method and ‘with’ construct to solve this problem

2

You can use the sum() method, but that only iterates over an unpacked array. You can create a dummy array just to use as an iterator.

rand bit [31:0] value;
bit itr[$bits(value)-1];
constraint c {
  itr.sum() with (int'(value[itr.index] != value[itr.index+1])) == 3;
}
3

Dave,
I believe there is a typo as well as missing int’ cast

constraint c { itr.sum() with( int'(value[item.index] != value[item.index+1]) ) == 3; }

For the highest item.index i.e 31 , shouldn’t there be an out of bound error/message as it tries to access index 32 which essentially doesn’t exist ?

EDIT: As Dave pointed below

bit itr[$bits(value)-1] ; // Same as bit itr[31] where Indexes iterate from 0 to 30
4

Thanks for catching me get caught by one of my own gotcha’s. Fixed.

Since I use [$bits(value)-1], the highest itr.index value is 30.