Is there any way to set a global solve...before?

SystemVerilog
, ,
1

Hello,
It’s being a while for me to write constraints, is there a way to create a global solve … before in SystemVerilog?

For example imagine I have a class:

class transaction;
  typedef enum {NORMAL, INVALID, PRESET1, PRESET2, ..., PRESETN} scenario_type;
  rand scenario_type scenario;
  rand int variable1;
  //...
  rand int variableN;
  constraint scenario_c {
        scenario dist {NORMAL:=70, PRESET1:=5, INVALID:=25}; //potentially many other types
  }
  constraint config_c {
    if (scenario = NORMAL) {
     variable1 inside {[MIN1 : MAX1]};
     //...
     variableN inside {[MINN : MAXN]};
    }
    if(scenario = INVALID) {
     variable1 inside {INVALID1};
     //...
     variableN inside {INVALIDN];
    }
    //Other cases for scenario values
  }
//...

endclass

In the above example I want make sure that scenario is solved always before any variable, so that variable1,…,variableN follow the values defined by the constraint config, but I do not want to write solve scenario before variable1,...,variableN

Any help is appreciated,
-R

2

There is no need for a solve before construct here. As long as there are no other conflicting dist construct, it has the same effect as the solve before in manipulating the distribution on results.

2 Likes