Debugging a complex constraint

SystemVerilog
,
1

Hi,

I am debugging a very complex constraint which has a lot of code and if-else statements.
I want some suggestions on how to debug it.

I tried the below approaches which do not work:

  1. Adding $display inside the constraint. My thinking was it will help me understand which if-else loop the code executes.
  2. Adding `uvm_info inside the constraint
  3. Using a variable and assigning it when it enters a loop. Something like this:
    constraint <> {
    if(<>) {
    loop_1_entered++;
    }
    }

Note: The constraint is passing, I need to understand what the constraint is doing.

Appreciate any suggestions!!

2

In reply to pswetalina:

You cannot use assignment operators (including ++) in a constraint expression. I prefer using boolean implication operators over uf/else constructs. Constrains are boolean expressions, not procedural code.

You should look at your tools user manual for help debugging constraint expressions.

3

Thanks Dave, I will check with the tool folks to see if there are any relevant switches.