I want to set one unpacked array equal to something in one line in the constraint. Can I do this in Systemverilog?
s1 -> a[2:5] == '{0,1,0,1}
this code has the simulation error.
In reply to Moein75:
Constraints involving random variables must be integral expressions. You must use iterative constraint like foreach or an array reduction method. In your example you are write it as
rand int a[10];
const int p[2:5] = {0,1,0,1};
constraint c {
s1 -> foreach(a[i]) {i inside {[2:5]} -> a[i] == p[I];};
}