Using String Type within a Constraint Expression

SystemVerilog
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1

Hi,

According to the LRM, is it illegal to use string type within a constraint expression?
Looks like Xcelium throws a compile-time error while Questa and VCS don’t.
If it’s actually illegal, may I know where it’s stated in the LRM?

class my_class;
  rand int idx;
  string opt[$] = { "a", "b", "c" };
  constraint c { opt[idx] != "a"; }
endclass: my_class

Best regards,
Jung Ik Moon

2

In reply to Jung Ik Moon:

This is an area of the LRM that needs some work and I hope to get to some of this in the next revision that just being started.

The LRM currently says

Constraints can be any SystemVerilog expression with variables and constants of integral type (e.g., bit, reg, logic, integer, enum, packed struct).

But then later section 18.5.13 Constraint guards clearly shows the use of other types being used on non-random state variables.

Another issue with the LRM and your example is the use of a random variable as an index to an unpacked array.

3

In reply to dave_59:

Hi Dave,

Thanks for the answer.

Best regards,
Jung Ik Moon