Hello, experts.
I tried to create a base sequence that included control knobs and constraints and inherited the base sequence to create various sequences, but there was a problem.
I got a constraint solver error and the error message is as follows during simulation running.
Error-[CNST-ICE] Constraint infeasible constraints error
As the solver has encountered a failure due to an infeasible set of
constraints, the values printed during this solve cycle are invalid.
The solver will preserve original values.
...
Error-[CNST-NPE] Constraint null pointer error
~~~error path~~~
Accessing null pointer cfg.sim_line in constraints.
Please make sure variable cfg.sim_line is allocated.
However, the configuration of the subsequence seems to be normal.
Maybe it's related to when the construction solver works.
I wonder if there is a solution.
The example code is provided below.
``` verilog
class my_config extends uvm_object;
`uvm_object_util(my_config)
function new(string name = "my_config")
super.new(name);
endfunction : new
int sim_line;
endclass : my_config
class base_seq extends uvm_sequence #(my_item);
`uvm_object_utils(base_seq)
// control knobs
rand bit [11:0] line_addr;
// configuration handle
my_config cfg;
// constraints
constraint line_addr_c {line_addr >=0; line_addr < cfg.sim_line;}
function new(string name = "base_seq")
super.new(name);
endfunction : new
virtual task pre_start();
if(!uvm_config_db #(my_config)::get(get_sequenceser(), get_sequence_path(), "cfg", cfg))
`uvm_fatal(get_type_name(), "Failed to get configuration")
endtask
endclass : base_seq
class nested_seq extends base_seq;
`uvm_object_utils(nested_seq)
sub_seq1 sub_seq1;
virtual task body();
`uvm_do_with(sub_seq1, {sub_seq1.line_addr == local::line_addr;}) // --> error occurs!
endtask : body
endclass : nested_seq
class sub_seq1 extends base_seq;
`uvm_object_utils(sub_seq1)
virtual task body();
// do something...
endtask : body
endclass : sub_seq1
class my_test extends uvm_test;
`uvm_component_utils(my_test)
function new(string name = "my_test", uvm_component parent);
super.new(name, parent);
endfunction : new
my_env env;
my_config cfg;
virtual function void build_phase(uvm_phase phase);
super.build_phase(phase);
env = my_env::type_id::create("env", this);
cfg = my_config::type_id::create("cfg"); // I forgot to write this line, sorry...
cfg.sim_line = 16; // I forgot to write this line, sorry...
uvm_config_db #(my_config)::set(this, "env.agt*", "cfg", cfg);
endfunction : build_phase
virtual task run_phase(uvm_phase phase);
nested_seq seq = nested_seq::type_id::create("seq");
phase.raise_objection(this);
seq.start(env.agt.sqr);
phase.drop_objection(this);
endtask : run_phase
endclass : my_test
```