Constraint solver error using the config object of subsequence in the nested sequence and subsequence that inherited the base sequence

UVM
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3

In reply to nhp:

Hi, nhp

Thank you for trying to solve the problem.

But I’m sorry, but there were some missing parts in the example code I posted.

The modified example code is below.

class my_config extends uvm_object;
    `uvm_object_util(my_config)
 
    function new(string name = "my_config")
        super.new(name);
    endfunction : new
 
    int sim_line; // modified
 
endclass : my_config

class my_test extends uvm_test;
    ...
    virtual function void build_phase(uvm_phase phase);
        super.build_phase(phase);
        env = my_env::type_id::create("env", this);
        cfg = my_config::type_id::create("cfg"); // I forgot to write this line, sorry...
        cfg.sim_line = 16; // I forgot to write this line, sorry...
        uvm_config_db #(my_config)::set(this, "env.agt*", "cfg", cfg);
    endfunction : build_phase
    ...
endclass : my_test

However, inspired by what you explained, I did some tests, and it seems that my constraint solver problem is related to when the config object was created.

Maybe your approach to the problem will be helpful.

So, I tried to add the line below.

function new(string name = “base_seq”);
super.new(name);
cfg = my_config::type_id::create(“cfg”, null);
endfunction : new

And I got an error below.

======================
Solver failed when solving following set of constraints
integer cfg.sim_line = 0;
rand bit[11:0] line_addr; // rand_mode = ON
constraint line_addr_c // (from this) (constraint_mode = ON) (~path~)
{
(line_addr < cfg.sim_line);
}
======================

I think for this error, sim_line = 16 setting was not passed to subsequence.

Thanks.