How constraint solver resolves conflicting constraints in dist?

SystemVerilog
, , ,
1 
class Transaction;
  rand bit read_write;
 
  constraint c1 { read_write dist {0:= 25, 1:= 75}; }
  constraint c2 { read_write dist {0:= 50, 1:= 2}; }
 
  function void pre_randomize();
    $display("Entering randomization \n");
  endfunction
 
  function void post_randomize();
    $display("Done with randomization \n");
  endfunction
endclass
 
module top;
 
  Transaction tr;
  int write_cnt, read_cnt;
  int constraint_status=0;
 
  initial begin
    tr = new;
    write_cnt = 0;
    read_cnt = 0;
    repeat(1000) begin
      assert(tr.randomize());
      constraint_status = tr.c1.constraint_mode();
      if(tr.read_write == 1) write_cnt++;
      else read_cnt++;
    end
    $display("Writes are %d, reads are %d, status is %d \n", write_cnt, read_cnt, constraint_status);
  end
 
endmodule

How is the constraint resolved here? I am getting

Writes are 422, reads are 578, status is 1

Also, when I have

constraint c1 { read_write dist {0:= 25, 1:= 75}; }
constraint c2 { read_write == 1'b1; }

The c2 constraint dominates and I get

Writes are 1000, reads are 0, status is 1

2

In reply to smukerji:

Absent any other constraints, the probability that the expression matches any value in the list is proportional to its specified weight. If there are constraints on some expressions that cause the distribution weights on these expressions to be not satisfiable, implementations are only required to satisfy the constraints. An exception to this rule is a weight of zero, which is treated as a constraint.

3

In reply to dave_59:

if there are conflicting constraints , what happens in this case ?

constraint c1 { read_write dist {0:= 25, 1:= 75}; }
constraint c2 { read_write dist {0:= 50, 1:= 2}; }

4

In reply to diptishe:

Undefined.