Assigning 1st element of enum as non-zero and accessing it

SystemVerilog
,
1

Hai all,

while declaring 1st element in enum as non-zero and accessing through it pointer is not working. if we assign the pointer with .first the code is working. what could be the reason


 module top;
 typedef enum {h01=1,h02,h03} alp;
 initial begin
  alp h1;
   //alp h1=h1.first  this is working
  $display(h1.name,h1);
  h1=h1.next;    
  $display(h1.name,h1);
  h1=h1.next;     
  $display(h1.name,h1);
  end 
  endmodule

output: (printing values oh h1. h1.name is not printing)
0
0
0

2

In reply to D Pavan Kalyan:

Assigning the initial value to h01 will solve the problem.

  alp h1 = h01;

Output:

h01          1
h02          2
h03          3

My understanding here is : The default init value in systemverilog is 0, and as 0 points to nothing/null in your enum; the display is 0. For the same reason the next operator doesn’t make sense either and it’s stuck at 0.

3

In reply to KillSteal:

Yes. But why without assigning it is not working. Is there any reason.

Incase of using 0 for first element this problem is not raising.

4

In reply to D Pavan Kalyan:

The default initial value of an enum is determined by its base datatype. not the first enumerated value. If the base datatype is int (the default base datatype) , the default initial value of the enum will be 0. This was done to allow you to declare an enum with a 4-state base datatype logic, whose default initial value is X.

If the current value of an enum variable is not one of the declared enumerated values, next() and prev() both return the default initial value which is 0 in your example.