Assigning 1st element of enum as non-zero and accessing it

SystemVerilog
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2

In reply to D Pavan Kalyan:

Assigning the initial value to h01 will solve the problem.

  alp h1 = h01;

Output:

h01          1
h02          2
h03          3

My understanding here is : The default init value in systemverilog is 0, and as 0 points to nothing/null in your enum; the display is 0. For the same reason the next operator doesn’t make sense either and it’s stuck at 0.