Defining array's range according to enumerated type attributes

SystemVerilog
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1

Hi.

I have an enumerated type e.g.


typedef enum logic[1:0] {
        FIRST,
        SECOND,
        THIRD,
        LAST
    } my_type;

I want to define one-hot vector (say a selector) accordingly without actually using the enumarated values.

I use the following method:


parameter my_type auxPrm = FIRST;
typedef logic [auxPrm.last():auxPrm.first()] one_hot_sel_vec_type;
...
one_hot_sel_vec_type one_hot_sel_vec;
...

Now, xilinx’s VIVADO is ok with this writing but synopsys’s synplify asserts an error:
“range’s bounds are not constant” referring to the “one_hot_sel_vec_type” definition which is weird because I intentionally defined a parameter “auxPrm” which is constant.

My question is then,
Am I wrong in my writing method?
Is there any other “right/standard” way of achieving the same result?

Thanks!
Itay.

2

In reply to itay yehekzel karo:
You have hit a tool specific issue. The only workaround is using the enum labels directly.

3

In reply to dave_59:

Thanks.
You mean its synplify’s error? the way of writing is allowed in the verilog standard?