Module instantiation from within a for-gen block, value of input port is not updating

SystemVerilog
, ,
1

Here’s the code:

module top;
  reg [1:0] in;
  wire [1:0] out;
  test #(.WIDTH(2)) a_inst(.in(2'b10), .out(out));
  initial $display("in[1]= %b", top.a_inst.GENBLOCK[1].ch.in);
endmodule

module test #(parameter WIDTH=4) (input [WIDTH-1:0] in, output [WIDTH-1:0] out);
  generate 
    for (genvar i = 0; i < WIDTH; i++) begin : GENBLOCK
      child #(.WIDTH(WIDTH),.BIT(i)) ch(in, out[i]);
    end
  endgenerate 
endmodule

module child #(parameter WIDTH=4, BIT=4) (input [WIDTH-1:0] in, output out);
  assign out = in[BIT];
  initial $display("%m: out = %b, in = %b, width = %2d, bit = %2d", out, in, WIDTH, BIT);
endmodule

I suppose child module should get the value of in = 2’b01, but it is X when is display the value.
Similary, i also changed inside generate block and changed the code like this:
for (genvar i = 0; i < WIDTH; i++) begin : GENBLOCK
child #(.WIDTH(WIDTH),.BIT(i)) ch(i, out[i]); //input is connected to genvar value
end
In this scenario as well, i am getting in = x in child module, however value of parameters in getting updated.

2

In reply to Kumar Saurabh:

Change your $display to a $strobe. Then look up what $strobe does.

3

In reply to dave_59:

Thank Dave.
With $strobe, it is displaying the expected value. It solved the issue.
It means, even if the module is instantiated with some fix value (instead of connection to any signal), it is only scheduled with other construct inside the module, isn’t it?

4

It’s mainly about exception of code in accordance to event queue. Your initial block and $display are scheduled to execute in the active region and hence the race condition. Because of the $strobe the value printed are the values at the end of the current time stamp. i.e stable value. You may even try to #0 delay before your $display that would also work but that is not a suggested way.

5

In reply to Kumar Saurabh:

Sometimes a port connection behaves like a continuous assignment between two signals. This usually happens when both sides of the port are not nets/wires. All continuous assignments get scheduled in the active region at time 0 simultaneously with all initial blocks. So you had a race condition with the $display.