Topics tagged parameter

Topic	Replies	Views	Activity
Assign parameter in interface SystemVerilog parameter , interface	5	214	February 18, 2024
Is it possibe to assign an int variable to an int parameter or not SystemVerilog SystemVerilog , System-Verilog , parameter , uvm-parameter-polymorphism	2	408	July 27, 2023
Passing array size as argument for another array inside the task/function SystemVerilog SystemVerilog , parameter , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	3	661	June 20, 2023
Can I static cast a "parameter int" to a "parameter string"? SystemVerilog SystemVerilog , parameter , casting	3	752	March 15, 2023
Usage of local parameter in a class SystemVerilog SystemVerilog , parameter	1	586	November 25, 2022
Parameter not being recognized in transaction class SystemVerilog SystemVerilog , parameter , Package-interdependecy	2	573	October 30, 2022
Generating an IO interface in a module based on parameter SystemVerilog SystemVerilog , System-Verilog , parameter	0	424	July 19, 2022
Facing Issue with Parameter override from top_tb UVM UVM , override , parameter , UVM-scoreboard	2	864	February 16, 2022
How to change parameter of systemverilog testbench with Makefille SystemVerilog SystemVerilog , testbench , parameter , makefile	1	1007	November 18, 2021
3 by 8 decoder SystemVerilog SystemVerilog , parameter , 3-by-8-decoder	1	908	April 12, 2021
Passing a parameter to a bind entity SystemVerilog SystemVerilog , bind , parameter	4	7502	August 28, 2020
SV bind in UVM where a parameter is used SystemVerilog SystemVerilog , UVM , parameter , SV-bind	10	7081	November 8, 2018
Parameter and generate usage in the interface SystemVerilog SystemVerilog , generate , parameter	2	1462	April 9, 2018
Which parameter is active when redefined? SystemVerilog SystemVerilog , parameter , redefine	7	2430	July 26, 2017
2-D dynamic array of parameters failed SystemVerilog SystemVerilog , parameter , Dynamic-Array	4	5405	June 19, 2017
UVM style suggestion needed for parameterized transactions/drivers UVM UVM , parameter , deterministic-sequence	2	2386	October 6, 2016
How to select appropriate package to import with a parameter? SystemVerilog SystemVerilog , parameter , import	3	3604	August 20, 2016
Reusable bind wrapper module SystemVerilog SystemVerilog , bind , parameter , module	0	1560	May 18, 2016
How to assign a variable name to a parameter? SystemVerilog SystemVerilog , parameter , array-of-defines	5	9240	May 4, 2016
Output/publish value of derived parameter for use in the next module SystemVerilog SystemVerilog , parameter , synthesize	3	1855	March 27, 2016
Pasing parameter values (for address width) to sequence item from Top module in UVM TB UVM UVM , parameter	1	1708	June 19, 2014
Why can't parameter class typedefs be used in variable declarations? SystemVerilog SystemVerilog , class , parameter , typedef	7	7090	February 19, 2014