Which parameter is active when redefined?

SystemVerilog
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1

When I define a parameter ADDR_WIDTH=10 in module A_top, and redefine it as 5 in module B; while module B is a inst in A_top.
Then the parameter ADDR_WIDTH is 10 or 5 when the code is running?

2

In reply to whwjez:

BTW, this is not what I want. How can VCS report a warning when this redefining situation happend by add some option?

3

In reply to whwjez:

This forum is not for tool specific help and cannot provide tool options.

Can you show an example piece of code and the behavior you are looking for? Maybe we can show you a standard way of doing what you want.

4

In reply to dave_59:


module A_top;
parameter ADDR_WIDTH = 10;

B  B_inst;
endmodule


module B;
parameter ADDR_WIDTH = 5;
endmodule

my question is that ADDR_WIDTH is defined twice, and what value is it finally?

5

In reply to whwjez:

each ‘ADDR_WIDTH’ is in its own scope…
B_inst will have 5, A will have 10

6

In reply to whwjez:

They remain independent parameters with independent values defined in separate scopes.

You would need to use a parameter override in the instantiation

B #(.ADDR_WIDTH(ADDR_WIDTH)) B_inst();

In that case 10 becomes the overriding value.

7

In reply to ssureshg_:

if B was overrided by A, like what dave_59 said above, then B will have 10, too

8

In reply to whwjez:

your original code has no overriding…