Verification Academy
Which parameter is active when redefined?
SystemVerilog
parameter
,
redefine
,
SystemVerilog
ssureshgverifier
July 26, 2017, 6:09am
5
In reply to
whwjez
:
each ‘ADDR_WIDTH’ is in its own scope…
B_inst will have 5, A will have 10
show post in topic