Output/publish value of derived parameter for use in the next module

SystemVerilog
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Is there a way in SystemVerilog to output the value of a parameter? I have a pipeline that accepts an input parameter and conditionally modifies that parameter. The next module in the pipeline needs the modified parameter, not the original parameter that was provided to the first module. There might be several stages in the pipeline, and it would be really great if I could output that value at each successive stage.

I know there is probably a very nice way to do this using non-synthesizable code, but I really need this to be synthesizable. Any ideas?

Thanks.

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In reply to slittle:

Can you show an example of how your modules are instantiated? I don’t normally think of a parameter as being an input. Perhaps you are thinking of a port when you say parameter.

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In reply to dave_59:

No, I am definitely not thinking of a port. I mean a parameter that needs to be successively updated in each module.

An analogous example of what I am trying to do would be something like fixed point mathematics. At each stage of processing, the data path width must grow according to the math that is performed in each module in the pipeline. For example, if I have two input arguments to a block that is performing addition, and those inputs are 2 bits wide, the output must have 3 bits to contain the result. So the parameter representing the width of the inputs must be modified and potentially passed out of the addition module for use in the next stage of processing.

What I am actually doing has nothing to do with this example, but fixed point is much easier to explain. I want to be able to modify a parameter at each stage in the design and pass that modified parameter out. But there is not any physical wire or bus width that is changing, only a parameter that relies on the previous value in the previous module. Right now I am doing this all manually, but it is very error prone.

Does that help explain the problem?

Thanks.

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In reply to slittle:

You can certainly define a parameter as expression of two other parameters. Can you show how these modules are instantiated and parameterized?