Topics tagged synthesize

Topic	Replies	Views	Activity
Synthesizable loop SystemVerilog SystemVerilog , synthesize , for-loop	1	4945	March 1, 2018
Which syntax can be Synthesized? SystemVerilog SystemVerilog , synthesize	6	2094	September 1, 2016
Output/publish value of derived parameter for use in the next module SystemVerilog SystemVerilog , parameter , synthesize	3	1917	March 27, 2016
Mod 10 in Verlig SystemVerilog SystemVerilog , Verilog , synthesize	1	2019	December 15, 2014