Pasing parameter values (for address width) to sequence item from Top module in UVM TB

UVM
,
1

There are a number of bit width (address and data widhts ) parameters declared in the my top module. These parameters are passed to the DUT instance and parameterized interface instances. How can I also pass these parameter values to the sequence items, so that the bit widths of the sequence item fields correspond to the bit widths of the interface fields?
MY DUT has parametarized ports.

Pls Let me know if there ia an easy sol with an example in UVM.

Thanks in Advance
Vijay

2

Since the bit-widths would have to be known at compile-time, you’ll need to declare your sequence item with parameters and register it with the factory using `uvm_object_param_utils.