How to create a parametrized assertion?

SystemVerilog
,
1

I am trying to create an assertion which checks whether a signal has been stable over the last n cycles (from when the assertion is evaluated).
I am trying to “parametrize the assertion” so that it can be applied to a signal of any width. I also want to put it in some package so that I can utilize it in any of my projects.
I am a beginner so I do not know SystemVerilog syntax extensively. I found an entry on stackoverflow relating to “Passing parameters to a Verilog function”. I drew some inspiration from it and came up with this:

package verification_pkg;
virtual class extended_stable # (parameter int n = 1, int WIDTH = 1);
static function automatic logic stable_for_n_cycles (
    input logic [WIDTH-1:0] sig
);
    if (n <= 1) begin
		return 1'b1;
    end

    for (int i = 1; i < n; i++) begin
		if ($past(sig, i) !== $past(sig, i-1)) begin
			return 1'b0;
		end
    end

    return 1'b1;
endfunction
endclass
endpackage

I know this won’t work. Among other reasons why, when sig is passed into stable_for_n_cycles, the function sees it as a logic value and no longer as a signal, so it no longer has a history and therefore it would not make sense to call $past from within the function.

That said, I still do not have any other idea on how to do this.

2

There is no need to write a function. SystemVerilog properties have all the syntax you need.

property stable_after_start(clk,rst,start, signal,N);
  @(posedge clk) disable iff (reset)
  $rose(start) |-> ##1 $stable(sig) [*N];
endproperty
3

Thanks a lot dave_59 for a quick response.

I am assuming you are using $rose(start) as the “trigger” condition at which the stability of sig gets evaluated?

So then what I still need to know is this:

What does this modifier [*N] mean?

1- For the previous N cycles? In this case it does the job.

2- For the next N cycles? In this case the property which you wrote does not fit what I have in mind.

4

Yes I did mean $rose.
[*N] means repeat the next N cycles.

This should do what you have in mind

module top;
  bit clk, rst, sig, st;

  property stable_after_start(clk,reset,start, signal,N);
    @(posedge clk) disable iff (reset)
      $rose(start) |-> ##1 $stable($past(signal,N)) [*N];
  endproperty
  
  initial #0.5ns repeat(100) #0.5ns clk = !clk;
  
  initial begin
    repeat (5) @(posedge clk);
    st <=1;   
    repeat (1) @(posedge clk);
    st <=0;
    repeat (5) @(posedge clk);
    sig <=1;
    repeat (1) @(posedge clk);
    st <= 1;
  end
  assert property (stable_after_start(clk,rst,st,sig,3)) $info("pass"); else $error("fail");
    
endmodule