3 by 8 decoder

SystemVerilog
, ,
1

How is this code implementing a 3 by 8 decoder?

module decoder #(parameter N = 3)  (input  logic [N–1:0]   a,   output logic [2**N–1:0] y); 
 always_comb  begin   
      y = 0;   y[a] = 1;
    end
endmodule
2

In reply to Shahrzad:

Please use code tags making your code easier to read. I have added them for you.

This is a very broad question. SystemVerilog code aside, do you know what a 3 to 8 decoder is supposed to do?