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    The Verification Academy offers users multiple entry points to find the information they need. One of these entry points is through Topic collections. These topics are industry standards that all design and verification engineers should recognize. While we continue to add new topics, users are encourage to further refine collection information to meet their specific interests.
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    The Verification Academy is organized into a collection of free online courses, focusing on various key aspects of advanced functional verification. Each course consists of multiple sessions—allowing the participant to pick and choose specific topics of interest, as well as revisit any specific topics for future reference. After completing a specific course, the participant should be armed with enough knowledge to then understand the necessary steps required for maturing their own organization’s skills and infrastructure on the specific topic of interest. The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization’s processes so that you can then reap the benefits that advanced functional verification offers.
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      • Introduction to ISO 26262
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      • An Introduction to Unit Testing with SVUnit
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    The Verification Academy Patterns Library contains a collection of solutions to many of today's verification problems. The patterns contained in the library span across the entire domain of verification (i.e., from specification to methodology to implementation—and across multiple verification engines such as formal, simulation, and emulation).
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    Find all the methodology you need in this comprehensive and vast collection. The UVM and Coverage Cookbooks contain dozens of informative, executable articles covering all aspects of UVM and Coverage.
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    No one argues that the challenges of verification are growing exponentially. What is needed to meet these challenges are tools, methodologies and processes that can help you transform your verification environment. These recorded seminars from Verification Academy trainers and users provide examples for adoption of new technologies and how to evolve your verification process.
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    The Verification Academy will provide you with a unique opportunity to develop an understanding of how to mature your organization's processes so that you can then reap the benefits that advanced functional verification offers.
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  • Please format your code with [code] and [/code] tags or [systemverilog] and [/systemverilog]

Please format your code with [code] and [/code] tags or [systemverilog] and [/systemverilog]

Announcements 153
dave_59
dave_59
Forum Moderator
8758 posts
October 29, 2014 at 7:28 am

Your source code will be much easier to read when it is formatted nice and pretty like this:
class packet;
   rand bit [31:0] data;
   rand bit [31:0] address;
   rand bit [7:0]  length;
   rand bit [7:0]  data[];

   constraint max_length {
      length == data.size();
   }
endclass: packet

instead of:

class packet;
rand bit [31:0] data;
rand bit [31:0] address;
rand bit [7:0] length;
rand bit [7:0] data[];

constraint max_length {
length == data.size();
}
endclass: packet

All you have to do is embed your code between [code] and [/code] tags, like this: (or use the <> button above the text input form)

[code]class packet;
   rand bit [31:0] data;
   rand bit [31:0] address;
   rand bit [7:0] length;
   rand bit [7:0] data[];

   constraint max_length {
      length == data.size();
   }
endclass: packet[/code]

You can also get syntax highlighting with tags [systemverilog] and [/systemverilog]

class packet;
   rand bit [31:0] data;
   rand bit [31:0] address;
   rand bit [7:0]  length;
   rand bit [7:0]  data[];
 
   constraint max_length {
      length == data.size();
   }
endclass: packet

You can also select the text you want to codify first, then click the <> button on the toolbar above the text editing pane.

— Dave Rich, Verification Architect, Siemens EDA

Replies

Log In to Reply
John Verif
John Verif
Full Access
145 posts
October 04, 2012 at 3:58 pm

Dave,
This tag looks awesome along with highlight.

Is there any plugin for VI editor/ nedit to format the code, do you aware of?

There is vim file to highlight the syntax.

John

dave_59
dave_59
Forum Moderator
8758 posts
October 04, 2012 at 11:38 pm

In reply to John Verif:

I know there are a number of browser plug-ins to add the tags. I'm not aware of anything specific for VI.

— Dave Rich, Verification Architect, Siemens EDA

John Verif
John Verif
Full Access
145 posts
March 07, 2013 at 1:08 pm

In reply to vishnuprasanth:

Why don't we have our own editors which helps us to write our verification code?

since we move-in in the direction of software, why don't we have editor which helps us on syntax and formatting.

Letz says, in JAVA developers have editors (which has intelligence), which brings the skeleton of the code and gives suggestions on syntax and highlights the errors when during coding itself.

We are not lesser than software developers. We are writing codes more than designers do.

Even vendors are not concentrating on this.

John

dave_59
dave_59
Forum Moderator
8758 posts
March 07, 2013 at 2:11 pm

In reply to John Verif:

Mentor has tools that help you write and analyze your verification source code. It understands class inheritance and has template generators to help you write your code (e.g. adds the proper constructors and factory registration to your o/uvm_objects and phase methods to your o/uvm_components). There are a number of tools available from other vendors to help you write your code.

Formatting code for posting in a web forum is a different issue. What I usually do is write the code in an editor that formats the code for me, copy&paste it into the post composing text box, then mark that as a code block using the little <> icon above the text box.

— Dave Rich, Verification Architect, Siemens EDA

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