Topics tagged systemverilog-Arrays-packedarrays-unpackedarrays

Topic	Replies	Views	Activity
System Verilog interview question SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes	5	2420	June 29, 2024
Passing array size as argument for another array inside the task/function SystemVerilog SystemVerilog , parameter , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	3	889	June 20, 2023
Constraint Randomization question SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes	8	4898	June 8, 2023
How to put unpacked array to systemverilog mailbox SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-mailbox	3	1735	April 23, 2023
Packed array to struct SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays	1	557	February 18, 2023
How to correctly use a Template function? SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays	1	859	February 15, 2023
Arrays SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays	3	558	November 9, 2022
$displayh SystemVerilog SystemVerilog , System-Verilog , systemverilog-Arrays-packedarrays-unpackedarrays	1	885	August 2, 2022
Packed arrays SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , uvm-packed-unpacked-array-SV	1	559	May 31, 2022
In Associative array, assign 50 random int values at random locations SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , associative_arrays	2	1049	May 25, 2022
Array constraint. Each row total should be 100, with each element less than 80. I want to understand how to do this using only sum method of array SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	9	1837	February 25, 2022
Passing Unpacked Array of Packed Array as task arguments SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	1	1325	February 23, 2022
Reverse an array without using the reverse() function SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-Arrays-logics	2	3305	October 28, 2021
Associative array duplicate items SystemVerilog SystemVerilog , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays	1	1571	October 27, 2021
SV questions for interviews - any additional answers are appreciated SystemVerilog SystemVerilog , constraint-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes , system-verilog-assertions-past-stable	1	2062	October 22, 2021
Randomizing packed array SystemVerilog SystemVerilog , array-slicing , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays , SV-systemVerilog-constraints-array , systemverilog-arrays-struct-constraint-randomization-indexes	5	1761	May 8, 2021
Err - A reference to a rand variable in an array index is not currently supported in this context SystemVerilog SystemVerilog , randomization , systemverilog-Arrays-packedarrays-unpackedarrays	5	1308	May 5, 2021
Why exported task or function can't have open arrays as a formal argument whereas imported function or task have? SystemVerilog SystemVerilog , DPI , export-DPI-C , systemverilog-Arrays-packedarrays-unpackedarrays , DPI-C-import-with-dynamic-array-as-argument	2	906	December 7, 2020
Assignment array with dependent on variable location SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays	1	513	June 24, 2020
Randomising a logic vector of more than 32 in System Verilog SystemVerilog SystemVerilog , randomization , array-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-constraint	5	3060	June 12, 2020
Using readmemh SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , readmemh , memory-read	3	12929	February 25, 2020
Use of a bit from a packed array as a ref to task SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays	6	2426	October 21, 2019
Compilation error using compare_field UVM SystemVerilog , UVM , systemverilog-Arrays-packedarrays-unpackedarrays	3	1284	October 17, 2019
AHB BUS Environment SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , Move-Memory-Class	1	1190	June 15, 2019
Usage of tick ( ' ) in array assignments -> packed vs unpacked SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays	3	17942	May 11, 2019
Packed and Unpacked Arrays SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays	4	3989	December 8, 2018
Unpacked/packed type assignment SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays	4	6267	November 2, 2018
How to write structural Logic in Class SystemVerilog SystemVerilog , DUT , checker , systemverilog-Arrays-packedarrays-unpackedarrays , uvm-verilog , StructuralModelling	2	1138	July 31, 2018
Array randomization SystemVerilog SystemVerilog , array-randomization , systemverilog-Arrays-packedarrays-unpackedarrays	2	1525	September 29, 2017
Difference between packed and unpacked arrays? SystemVerilog SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays	1	2165	September 17, 2017

System Verilog interview question

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes

5

2420

June 29, 2024

Passing array size as argument for another array inside the task/function

SystemVerilog

SystemVerilog , parameter , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays

3

889

June 20, 2023

Constraint Randomization question

SystemVerilog

SystemVerilog , constraint-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes

8

4898

June 8, 2023

How to put unpacked array to systemverilog mailbox

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-mailbox

3

1735

April 23, 2023

Packed array to struct

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays

1

557

February 18, 2023

How to correctly use a Template function?

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays

1

859

February 15, 2023

Arrays

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays

3

558

November 9, 2022

$displayh

SystemVerilog

SystemVerilog , System-Verilog , systemverilog-Arrays-packedarrays-unpackedarrays

1

885

August 2, 2022

Packed arrays

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , uvm-packed-unpacked-array-SV

1

559

May 31, 2022

In Associative array, assign 50 random int values at random locations

SystemVerilog

SystemVerilog , constraint-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , associative_arrays

2

1049

May 25, 2022

Array constraint. Each row total should be 100, with each element less than 80. I want to understand how to do this using only sum method of array

SystemVerilog

SystemVerilog , constraint-randomization , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays

9

1837

February 25, 2022

Passing Unpacked Array of Packed Array as task arguments

SystemVerilog

SystemVerilog , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays

1

1325

February 23, 2022

Reverse an array without using the reverse() function

SystemVerilog

SystemVerilog , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-Arrays-logics

2

3305

October 28, 2021

Associative array duplicate items

SystemVerilog

SystemVerilog , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays

1

1571

October 27, 2021

SV questions for interviews - any additional answers are appreciated

SystemVerilog

SystemVerilog , constraint-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-arrays-struct-constraint-randomization-indexes , system-verilog-assertions-past-stable

1

2062

October 22, 2021

Randomizing packed array

SystemVerilog

SystemVerilog , array-slicing , systemverilog-Arrays , systemverilog-Arrays-packedarrays-unpackedarrays , SV-systemVerilog-constraints-array , systemverilog-arrays-struct-constraint-randomization-indexes

5

1761

May 8, 2021

Err - A reference to a rand variable in an array index is not currently supported in this context

SystemVerilog

SystemVerilog , randomization , systemverilog-Arrays-packedarrays-unpackedarrays

5

1308

May 5, 2021

Why exported task or function can't have open arrays as a formal argument whereas imported function or task have?

SystemVerilog

SystemVerilog , DPI , export-DPI-C , systemverilog-Arrays-packedarrays-unpackedarrays , DPI-C-import-with-dynamic-array-as-argument

2

906

December 7, 2020

Assignment array with dependent on variable location

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays

1

513

June 24, 2020

Randomising a logic vector of more than 32 in System Verilog

SystemVerilog

SystemVerilog , randomization , array-randomization , systemverilog-Arrays-packedarrays-unpackedarrays , systemverilog-constraint

5

3060

June 12, 2020

Using readmemh

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , readmemh , memory-read

3

12929

February 25, 2020

Use of a bit from a packed array as a ref to task

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays

6

2426

October 21, 2019

Compilation error using compare_field

UVM

SystemVerilog , UVM , systemverilog-Arrays-packedarrays-unpackedarrays

3

1284

October 17, 2019

AHB BUS Environment

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays , Move-Memory-Class

1

1190

June 15, 2019

Usage of tick ( ' ) in array assignments -> packed vs unpacked

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays

3

17942

May 11, 2019

Packed and Unpacked Arrays

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays

4

3989

December 8, 2018

Unpacked/packed type assignment

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays

4

6267

November 2, 2018

How to write structural Logic in Class

SystemVerilog

SystemVerilog , DUT , checker , systemverilog-Arrays-packedarrays-unpackedarrays , uvm-verilog , StructuralModelling

2

1138

July 31, 2018

Array randomization

SystemVerilog

SystemVerilog , array-randomization , systemverilog-Arrays-packedarrays-unpackedarrays

2

1525

September 29, 2017

Difference between packed and unpacked arrays?

SystemVerilog

SystemVerilog , systemverilog-Arrays-packedarrays-unpackedarrays

1

2165

September 17, 2017